ECE 443: Hardware Design with VHDL

Instructor: Jim Plusquellic
COSMIAC Representative: Craig Kief
Department of ECE, UNM


* Course Syllabus

* Course Introduction
* VHDL Overview
* VHDL Basics
* Concurrent Signal Assignment
* Sequential Statements
* VHDL Synthesis
* Combinational Design
* Sequential Design: Principles
* Sequential Design: Practice
* Finite State Machines
* RTL: Principles
* RTL: Practice

Supplimentary Slide Sets:

* Xilinx generated schematics from lecture slides
* UART documentation and VHDL code
* VGA documentation and VHDL code

Extra/Alternative Slide Sets:

* EXTRA: VHDL Intro
* Programmable Logic Devices I
* Programmable Logic Devices II
* Programmable Logic Devices III
* Programmable Logic Devices IV
* SRAM Design Unit

Wiki Page: VHDL and FPGAs at UNM:

* VHDL & FPGA Wiki page
* Video Lecture: UART: Part 1
* Video Lecture: UART, Part 2
* Video Lecture: UART, Part 3
* Video Lecture: UART, Part 4
* Video Lecture: VHDL Basics
* Video Lecture: Synthesis of VHDL: Part 1
* Video Lecture: Synthesis of VHDL, Part 2
* Video Lecture: VGA
* Video Lecture: Combinational Circuit Design, Part 1
* Video Lecture: Combinational Circuit Design, Part 2
* Video Lecture: Combinational Circuit Design (Part 3) and Sequential Circuit Design (Part 1)
* Video Lecture: Sequential Circuit Design, Part 2
* Video Lecture: Sequential Circuit Design, Part 3
* Video Lecture: Sequential Circuit Design, Part 4
* Video Lecture: Sequential Circuit Design, Part 5
* Video Lecture: Finite State Machines, Part 1
* Video Lecture: Finite State Machines, Part 2
* Video Lecture: Finite State Machines, Part 3
* Video Lecture: Finite State Machines, Part 4
* Video Lecture: Finite State Machines, Part 5
* Video Lecture: RTL Design, Part 1
* Video Lecture: RTL Design, Part 2
* Video Lecture: RTL Design, Part 3
* Video Lecture: RTL Design, Part 4
* Video Lecture: Guest Lecture 1
* Video Lecture: Guest Lecture 2

Announcements:

* PLEASE BE REMINDED THAT class will meet at 10AM, Dec. 11th (instead of 2PM) in the same room. The first group of demos will be done at that time.
* !!!!!!!!!!!!!!!!!!!!!!!! CLASS IS CANCELLED Thur., Dec 6th !!!!!!!!!!!!!!!!!!!!!!!!!!
* !!!!!!!!!!!!!!!!!!!!!!!! CLASS IS CANCELLED Tue., Nov 27th and Thurs., Nov. 29th !!!!!!!!!!!!!!!!!!!!!!!!!!
* 10/3/2012: MID-TERM exam to be held on Thurs., Oct. 18th. COVERS Slide sets: VHDL Overview
VHDL Basics
Concurrent Signal Assignment
Sequential Statements
Combinational Design -- upto and including slide 21
Sequential Design: Principles
Sequential Design: Practice
UART documentation and VHDL code
VGA documentation and VHDL code -- upto slide and including slide 33

Links:

* COSMIAC and their tutorials
* Prof. Pong Chu's slides

Configuration Files:

* Nexys2 Reference Manual
* Nexys2 Schematic
* Nexys2 UCF (500)
* Nexys2 UCF (1200)
* Registration ID
* Digilent NEXYS2 (required purchase: $99)
* Xilinx ISE WEBPACK (required: $0, download Version 12.4)
* USB to Serial driver

Laboratory Notes:

* LABORATORY GRADING CRITERIA

Laboratories:

* Lab1
* Lab2
* Lab2 Files (7-segment display driver)
* Lab3
* Lab3 Files (SerialInterface, UART, FIFO, etc)
* Lab4 (NEW DUE DATE: Tue Oct. 16)

Project:

* First part of the project due on 11/12/2012. As I mentioned in class, you need to show in your demo some portion of the game you decided to implement. This will include background graphics + something moving in the forground.
* Please be prepared to do a 'progress' demo on Tue. Nov. 20th, and Dec. 3rd (Class is cancelled Nov. 27 and 29). Progress demos just need to show you are making progress.
* It is forbidden to download ANY PART of your game from public sites. Cheating will be dealt with harshly, with both members of the group failing the project portion of your grade.
* FINAL DEMOS: Each group will be allocated 15 minutes on Dec. 11 and 13 to demo their games (5 minutes) and to give a 10 minute briefing on the overall design and challenges you faced in developing the game. Either a power point or pdf presentation is fine. Presentation should include a block diagram that shows the organization of the game as a set of modules, and some VHDL code fragments that represent the core component(s). You need to turn in a printed copy of the VHDL code and presentation so that I can look it over. Selected groups will be asked to turn in an electronic version of the VHDL code, project files, etc. The schedule of demos will be discussed in class on Nov. 20th and Dec. 3rd.
Jim Plusquellic / ECE /